Cadence Design Systems announced that its design environment has achieved Design Rule Manual (DRM) and SPICE certification for Tsmc's latest N6 and N5 process technologies. These advances enable the development of next-generation mobile applications on N6 and N5 and hyperscale applications on N5 with updated reference flows and methodologies. Cadence and Tsmc are working globally with customers on manufacturing projects based on TSMC's advanced processes, including N7, N6 and N5, and have already achieved working tapeouts. The certified tool suites support the Cadence Intelligent System Design strategy, which enables customers to achieve excellence in SoC design. The integrated Cadence flow ensures total convergence, allowing all tools to work seamlessly together. Customers can download the corresponding N6 and N5 process design kits (PDKs) to start designing immediately.
