Cadence Design Systems has expanded its long-standing collaboration with Arm to promote the development of mobile devices based on Arm® Cortex®-A78 and Cortex-X1 CPUs. To drive adoption of Cortex-A78 and Cortex-X1 technology, Cadence has developed a comprehensive digital Rapid Adoption Kit (RAK) that helps customers optimize power, performance and area (PPA) and increase overall productivity. In addition, the Cadence® Verification Suite and its engines have been optimised for Cortex-A78 and Cortex-X1 CPU-based designs, providing engineers with improved verification throughput.
Cadence and Arm, a partnership in the interest of customers
Cadence's customers are represented by the world's most innovative companies, whose products address applications in the most dynamic markets, from 5G communications to medical. As Nimish Modi, senior vice president, marketing and business development at Cadence, said: "Over the past few years, we have worked closely with Arm to ensure that our solutions - the digital RAK Full Flow and Verification Suite and engine - are optimised for the Cortex-A78 and Cortex-X1 CPUs. Customers are under constant pressure to deliver innovative mobile technologies on time and our collaboration allows them to deploy Arm cpu's faster while achieving their quality goals."
The digital Full Flow RAK
Cadence's digital Full Flow RAK has been optimised for optimum power and performance levels. The solution supports 7nm and 5nm process nodes. Cadence's fully integrated RTL-to-GDS RAK includes the Genus™ synthesis solution, Innovus™ implementation system, Quantus™ extraction solution, Tempus™ Timing Signoff and ECO solutions, and Voltus™ Power Integrity IC solution. Key features integrated into the complete digital flow include:
- iSpatial Cadence technology, which unifies the Genus synthesis solution and the Innovus implementation system to deliver higher levels of PPA and faster design closure;
- Power optimisation based on vector-driven RTL-to-signoff tasks, enabling designers to achieve lower power consumption for critical workloads;
- simultaneous closure of power integrity and timing signoff using Cadence's unique data model, which integrates implementation, timing signoff and IR drop, essential for design on advanced 5nm and 7nm process nodes.
Engine and verification suite
To support designs based on Arm Cortex-A78 and Cortex-X1 CPUs, and to increase verification productivity, Cadence has also optimised the combination of the Cadence Verification Suite and its engines. The Cortex-A78 and Cortex-X1 CPU-optimised suite includes the Cadence Xcelium™ logic simulation platform, the Palladiun® Z1 Enterprise emulation platform, the JasperGold® formal verification platform, the vManager™ planning and measurement solution, and the Cadence Arm AMBA® VIP including CIP ACE and CHI-D and the Arm Perspec®System Verifier library.
Some of the key technologies supporting development on Cortex-A78 and Cortex-X1 are the JasperGold Formal Property Verification (FPV) and Sequential Equivalence Checking (SEC) apps, which have been used in lock-step verification to achieve deterministic results in multi-core verification. In addition, the Verification Suite's dynamic engines were used by joint customers for verification and preliminary software development.
Paul Williamson, vice president and general manager, Client Line of Business at Arm, commented, "Cadence's RAK and Verification Suite gives customers the foundation they need to develop next-generation mobile devices with our Cortex-A78 and Cortex-X1 CPUs, which will enable our partners to transform the smartphone experience in the 5G era.
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